The present invention relates to methods of fabricating a metal-insulator-metal (MIM) capacitor, and more particularly, to methods of forming a MIM capacitor having interdigitated capacitor plates.
The fabrication of semiconductor devices would benefit from increasing the capacity density of MIM capacitors because a greater capacity density yields a higher capacitance per unit of chip area. This higher capacitance per unit of chip area would allow MIM capacitors to have a smaller area, which permits greater compacting of semiconductor chips through space savings.
MIM capacitors are capacitors typically built into the back end of the line (BEOL) of a chip, which tend to have very good performance properties compared to front end of the line (FEOL) capacitors. Also, MIM capacitors do not consume space on the silicon, and typically do not consume space in wiring levels. This makes MIM capacitors an attractive option for integrated circuit design. However, they do cost extra processing and extra mask levels.
Conventional MIM capacitors require 1 lithographic level per capacitor plate. Since a capacitor requires a minimum of 2 plates, MIM capacitors will thus require at least 2 plates. Integration schemes to use 3 or more interdigitated capacitor plates can become very complicated and costly.
MIM capacitors have been disclosed generally in Tu et al. U.S. Pat. No. 7,115,935, Tu Patent Application Publication US 2005/0124132 and Chou et al. U.S. Patent Application Publication US 2006/0148192, the disclosures of which are incorporated by reference herein.
Coolbaugh et al. U.S. Patent Application Publication US 2003/0197215, the disclosure of which is incorporated by reference herein, discloses a stacked capacitor arrangement in which the capacitor layers are staggered so that each capacitor layer may be connected to a wiring by a via.